1. Field of Invention
The invention relates to the manufacture of integrated circuits and, more particularly, to processes and materials for the fabrication of dual damascene integrated circuit features.
2. Description of the Prior Art
The near-universal trend in the manufacture of integrated circuits (ICs) is towards producing ICs having smaller device dimensions and increased circuit densities. Increasing circuit density results in current-carrying elements lying in close proximity, which tends to increase electronic cross-talk between nearby circuit elements, among other deleterious effects on circuit performance. Decreasing component size includes decreasing the cross-sections of metal interconnection elements (“interconnects”), thereby increasing resistance heating and otherwise hindering circuit performance. Efforts to ameliorate the deleterious effects of increased component densities and decreased interconnect cross-sections include the use of insulating materials with lower dielectric constants than typical oxide insulators (“low k materials”), and the use of conducting materials with higher conductivity than typical aluminum (Al) conductors. Copper is emerging as the leading material for use as the on-chip conductor in typical present-generation ICs.
Copper (Cu) as a high-conductivity conductor in ICs can improve the electronic performance of the circuits but also has disadvantages in comparison with Al. For example, Cu readily diffuses through silicon dioxide, SiO2, the typical inter metal insulator used in ICs. If Cu diffuses into the silicon semiconductor substrate, the electronic properties of the semiconductor can be damaged resulting in degradation of circuit performance or failure of the IC. Also, Cu does not adhere very well to SiO2, complicating the use of Cu for IC interconnects in the presence of oxide insulators. For these and other reasons, the deposition of Cu is typically preceded by the deposition of one or more barrier/adhesion layers for the dual purpose of preventing Cu diffusion and enhancing adhesion. Tantalum/Tantalum Nitride (Ta/TaN) is a typical material used for barrier/adhesion layers in contact with Cu conductors.
In addition to the need for barrier/adhesion layers, Cu presents challenges to precise patterning and etching. For example, Cu does not readily form volatile chlorides or fluorides, rendering typical plasma etching based upon chlorine and/or fluorine chemistries impracticably slow. Thus, subtractive patterning of Cu, in which a Cu layer is selectively etched away below a patterned layer of photoresist, has been largely replaced by “damascene” or “dual damascene” patterning. The resulting IC structures or features are referred to as damascene or dual damascene structures or features.
Damascene patterning typically includes the photo lithographic creation of a pattern in one or more layers of insulator followed by a blanket deposition of the Cu or other interconnect material (preceded by the deposit of barrier/adhesion layer(s) if necessary). The deposited metal typically fills the patterned features in the insulator as well as coats the field regions between features. Metal coating on the field region can be removed by chemical-mechanical-planarization (“CMP”) or other techniques, exposing the metal-filled features in the insulator for further coating or other processing. Thus, a pattern of interconnects is created in the insulator without the need for etching a pattern directly into Cu or other metal.
Dual damascene denotes the fabrication of multi-layer features in the insulator before metal is deposited. Thus, a combination of trenches and holes (“visa”) can be fabricated in one or more insulating layers by the use of multiple patterning and etching steps preceding the deposit of metal. Planarization and removal of metal from the field region is then performed substantially as in the damascene fabrication of features.
Problems can occur in the patterning and the fabrication of features in ICs as a result of reflection of the exposing radiation from the surface (or surfaces) lying below the layer of photoresist. For example, interferences of incident and reflected radiation occurring within the layer of photoresist lead to non-uniform photoresist exposure and imprecise patterning. In addition, exposing radiation can reflect from surface topography or regions of non-uniform reflectivity resulting in exposure of photoresist in regions lying beneath the photo mask and for which exposure is not desired. In both cases, variations in the feature critical dimensions (“CDs”) can occur, adding to the challenges of precise and reproducible fabrication of IC features.
A common practice to eliminate or reduce fabrication problems resulting from radiation reflection is the use of anti-reflective coatings. In particular, Bottom-Anti reflective-Coatings (“BARCBS”) are commonly applied beneath the photoresist layer, lying on the surface to be patterned. BARC layers may be designed to absorb radiation that penetrates the layer of photoresist and, by this mechanism, reduce or eliminate the deleterious effects of reflections from the underlying surface. In addition, BARC layers may be designed through choice of BARC material and thickness such that, at the wavelength of the exposing radiation, destructive interference occurs between incident and reflected radiation. Both absorptive and destructive interference effects may be used in the same BARC layer.
However, BARC materials are typically organic materials that commonly etch at different rates from the surrounding insulator (oxide) material. With oxide etching typically performed by means of fluorocarbon chemistries, BARCBS tend to etch at slower rates than the surrounding oxide. This difference in etching often results in the presence of protrusions (“fences” or “fencing”) surrounding regions of unetched BARC material. Fences are undesirable for several reasons, including the fact that they are difficult to coat uniformly with material to form a uniform, conform al coating of barrier/adhesion layer. That is, good step-coating in the presence of fencing is hard to achieve with typical physical vapor deposition (PVD) due in large part to shadowing effects of the fencing. Gaps in the coating often result. Incomplete coating with barrier/adhesion layer, followed by Cu deposition, can result in diffusion of the Cu into the silicon regions of the IC, improper electronic performance and possible rejection of the IC.
Thus, a need exists in the art for etching IC features in the presence of BARC layers and the elimination of fencing that typically results therefrom.